Skip to Main Content
Chopping technique is an efficient approach to decrease the 1/f noise and low-frequency offset of CMOS amplifiers, but conventional chopper amplifier consumes large power because it required a wide-band amplifier exceed a chopping frequency and a post low pass filter (LPF) for eliminating modulation noise. In this paper, an improved chopper amplifier for reducing power consumption is presented which is composed of a two-stage amplifier. The high output impedance of the first stage folded cascode amplifier and the equivalent Miller capacitance constitute together a LPF to filter out the modulation noise, so the chopper amplifier need not the post LPF, which can reduce the power consumption. The circuit of the presented chopper amplifier is designed in TSMC 0.18μm CMOS technology. The chopper amplifier consumes 20 μA current and 36 μW power at 1.8V supply. The equivalent input noise voltage is 73nV/√(Hz) @1Hz and the input noise voltage integrated from 0.1Hz to 150Hz is 0.68μV rms.
Date of Conference: 6-9 Dec. 2010