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A 26 \mu W 8 bit 10 MS/s Asynchronous SAR ADC for Low Energy Radios

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8 Author(s)
Harpe, P.J.A. ; Hoist Centre, imec, Eindhoven, Netherlands ; Zhou, C. ; Yu Bi ; van der Meijs, N.P.
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This paper presents an asynchronous SAR ADC for flexible, low energy radios. To achieve excellent power efficiency for a relatively moderate resolution, various techniques are introduced to reduce the power consumption: custom-designed 0.5 fF unit capacitors minimize the analog power consumption while asynchronous dynamic logic minimizes the digital power consumption. The variability of the custom-designed capacitors is estimated by a specialized CAD tool and verified by chip measurements. An implemented 8-bit prototype in a 90 nm CMOS technology occupies 228 μm × 240 μm including decoupling capacitors, and achieves an ENOB of 7.77 bit at a sampling frequency of 10.24 MS/s. The power consumption equals 26.3 μW from a 1 V supply, thus resulting in an energy efficiency of 12 fJ/conversion-step. Moreover, the fully dynamic design, which is optimized for low-leakage, leads to a standby power consumption of 6 nW. In that way, the energy efficiency of this converter can be maintained down to very low sampling rates.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:46 ,  Issue: 7 )