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A 1.8 \mu W 60 nV /\surd Hz Capacitively-Coupled Chopper Instrumentation Amplifier in 65 nm CMOS for Wireless Sensor Nodes

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4 Author(s)
Qinwen Fan ; Delft Univ. of Technol., Delft, Netherlands ; Sebastiano, F. ; Huijsing, J.H. ; Makinwa, K.A.A.

This paper presents a low-power precision instrumentation amplifier intended for use in wireless sensor nodes. It employs a capacitively-coupled chopper topology to achieve a rail-to-rail input common-mode range as well as high power efficiency. A positive feedback loop is employed to boost its input impedance, while a ripple reduction loop suppresses the chopping ripple. To facilitate bio-potential sensing, an optional DC servo loop may be employed to suppress electrode offset. The IA achieves 1 μV offset, 0.16% gain inaccuracy, 134 dB CMRR, 120 dB PSRR and a noise efficiency factor of 3.3. The instrumentation amplifier was implemented in a 65 nm CMOS technology. It occupies only 0.1 mm2 chip area (0.2 mm2 with the DC servo loop) and consumes 1.8 μA current (2.1 μA with the DC servo loop) from a 1 V supply.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:46 ,  Issue: 7 )