By Topic

Key Aspects in Modeling of Thin Epi SOS Technology With Application of BSIMSOI

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
Roach, J. ; Peregrine Semicond., San Diego, CA, USA ; Lee-Wen Chen ; Clarke, P. ; Dikshit, A.
more authors

This work addresses the device modeling challenges of production-quality, state-of-the-art, silicon-on-sapphire (SOS) processes. Differences between SOS, silicon-on-insulator (SOI), and bulk CMOS are highlighted, with emphasis on the key differences in the modeling methodology. For RF and low-power applications, SOS has distinct advantages over SOI, such as reduced parasitics, better linearity, and enhanced electrical isolation. Yet little is reported in the literature about modeling of a commercially viable SOS process. Though originally developed for SOI, it is demonstrated that the BSIMSOI model can adequately represent SOS MOSFETs, including fully and partially depleted devices. For RF switch applications, RON and COFF are captured with reasonable accuracy. An additional RF figure of merit, fT, is also reasonably well modeled, yielding peak values in the 40-50 GHz range.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:46 ,  Issue: 5 )