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This paper presents a CMOS single-ended power amplifier for UHF RFID reader system-on-chip. Since the power amplifier for RFID reader demands high power gain and linearity, the designed power amplifier adopts two-stage structure which has a class-A operation. The power amplifier is designed and fabricated using commercial 0.13 μm CMOS process. Its chip size is 500×420 μm2. It is operated at a frequency range of 900 MHz with a supply voltage of 3.3 V. The measured output 1-dB compression point (P1dB) and power gain with a single-tone input are 17.7 dBm and 31.7 dB, respectively. A power-added efficiency (PAE) at P1dB is about 27 %. A 3rd-order intermodulation distortion (IMD3) of lower than -30 dBc is maintained up to 14.06 dBm for an output power. The maximum output 3rd-order intercept point (OIP3) was measured by 27.32 dBm at an output power of 11.27 dBm.
Date of Conference: 13-16 Feb. 2011