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In high-speed nanometre VLSI technology, the on-chip interconnect delay plays an important role and is dominant compared to the gate delay. Hence, an accurate estimation of the on-chip interconnect delay dictates both performance and physical design optimization for high speed CMOS VLSI circuits. The interconnect is modelled as distributed segments which ensures the system order to be in millions. An accurate and detailed modelling requires large scale linear circuits to be analyzed. Accurate estimation of the propagation delay of such a large circuit is critical. Therefore, a method of reducing the circuit order (or size) is necessary in order to compute the propagation delay in a reasonable time period which might not be exact, but nearly exact delay estimate, as required from the designer's point of view. This paper presents a simple and yet accurate delay modelling approach using the Balanced Truncation Method (BTM) for the on-chip distributed RLC interconnects. The proposed delay can be estimated as a closed form from the state space model for an evenly distributed RLC truncated interconnects. The closed form has very low computation complexity of O(1), which may be extended for use not only in circuits, but also in various complex systems with transmission lines, networks or delay lines. The proposed model could result an error of as low as 9% when compared to that of the SPICE simulation.