Skip to Main Content
Several approaches to design a linear attenuator have been analyzed in terms of the transistor impedance variation, linearity, frequency responses, and circuit complexity. This paper proposes a novel method of using an adaptive bootstrapped body biasing. The method allows the attenuator to have maximum power handling capability and bandwidth without adding complexity to the circuit. A π-type variable attenuator for WCDMA transmitters has been designed and fabricated using IBM 0.18-μ m triple-well CMOS technology. The attenuator has a linear-in-dB controllability from 400 MHz to 3.7 GHz with an attenuation range of 33 dB. Its insertion loss is 0.9-2.9 dB and worst-case return loss is better than -9 dB within this frequency band. The minimum input 1-dB compression point (IP1dB) is above 7.5 dBm, and the minimum IIP3 is greater than 17 dBm at 1.95 GHz. To our knowledge, this design achieves the best linearity performance and frequency responses, and has the smallest area among similar CMOS works.
Date of Publication: May 2011