Design methodology for the IBM POWER7 microprocessor

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The IBM POWER7® microprocessor, which is the next-generation IBM POWER® processor, leverages IBM's 45-nm silicon-on-insulator (SOI) process with embedded dynamic random access memory to achieve industry-leading performance. To deliver this complex 567-$hbox{mm}^{2}$ die, the IBM design team made significant innovations in chip design methodology. This paper describes the most critical methodology innovations specific to POWER7 design, which were in modularity, timing closure, and design efficiency.

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Published in:
IBM Journal of Research and Development (Volume:55 , Issue: 3 )

Date of Publication: May-June 2011

Page(s):: 9:1 - 9:14
ISSN :: 0018-8646
Digital Object Identifier :: 10.1147/JRD.2011.2105692
Product Type:: Journals & Magazines

Date of Current Version :: 14 March 2011
Issue Date :: May-June 2011
Sponsored by :: IBM

Author(s)

Friedrich, J.
IBM Systems and Technology Group, Austin, TX, USA
Puri, R. ; Brandt, U. ; Buehler, M. ; DiLullo, J. ; Hopkins, J. ; Hossain, M. ; Kazda, M. ; Keinert, J. ; Kurzum, Z.M. ; Lamb, D. ; Lee, A. ; Musante, F. ; Noack, J. ; Osler, P.J. ; Posluszny, S. ; Qian, H. ; Ramji, S. ; Rao, V. ; Reddy, L.N. ; Ren, H. ; Rosser, T. ; Russell, B.R. ; Sze, C. ; Tellez, G.