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Fast-access BiCMOS SRAM architecture with a VSS generator

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4 Author(s)

A fast-access intermediate supply voltage level BiCMOS SRAM (ISVOL) architecture is proposed for advancing circuit technology to megabit-level SRAMs using low-submicron MOSFETs. To verify this concept's effectiveness, a 256-kb SRAM, with a typical access time of 5 ns, is evaluated and reported. The access time dependence of the supply voltage is shown. This architecture can suppress the access time variance to within 4% for a 15% supply voltage variation

Published in:

VLSI Circuits, 1990. Digest of Technical Papers., 1990 Symposium on

Date of Conference:

7-9 June 1990