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A high-speed sample-and-hold technique using a Miller hold capacitance

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2 Author(s)

A technique for increasing the precision of open-loop sample-and-hold circuits without significantly reducing their sampling rate is introduced. With this technique, the sampling error resulting from input-dependent charge injection in the sampling switch is significantly attenuated by sampling the input voltage onto a capacitance that is small during the sample mode but is, in effect, increased during the hold mode through the use of Miller feedback. A sample-and-hold circuit based on this approach has been designed and fabricated in a 1-μm CMOS technology, and an order-of-magnitude reduction in the input-dependent charge injection has been verified experimentally. This circuit is capable of sampling an input to a precision of 8 b with an acquisition time of only 5 ns

Published in:

VLSI Circuits, 1990. Digest of Technical Papers., 1990 Symposium on

Date of Conference:

7-9 June 1990