Skip to Main Content
High speed and low power SBOX for Advanced Encryption Standard (AES) is proposed in this paper. Composite Galois Field is used in SBOX architecture to reduce size and delay of the circuit. Transmission gate is employed to reduce power consumption of the circuit. The proposed SBOX architecture consumes 186μw at 10MHz. The delay is reduced by 28.1%, and the average power consumption is reduced by 68.8% as compared to CMOS standard cell composite field design.
Design and Test Workshop (IDT), 2010 5th International
Date of Conference: 14-15 Dec. 2010