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Quick address detection of anomalous memory cells in a flash memory test structure

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7 Author(s)
Himeno, T. ; Microelectron. Eng. Lab., Toshiba Corp., Yokohama, Japan ; Hazama, H. ; Yaegashi, T. ; Sakui, K.
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A novel scheme for quick address detection of anomalous memory cells having the highest and lowest threshold voltages in a flash memory test structure is described. A test structure with a large memory cell array has been developed to evaluate reliability of flash memory cells before fabrication of a new generation of flash memory devices. In this test structure, each terminal branch of a tree-structured column selector is connected to each bitline of the array. And a simple threshold voltage distribution monitor circuit (VTDM) which we have already proposed is connected to the other end of the bitlines. A proposed Multi-Address Scanning Scheme (MASS) is performed by the tree-structured column selector with monitoring the output of VTDM. The detection time has been reduced to 1.12% in the case of 2048 columns. This novel scheme is suitable for performing reliability tests, such as program/erase endurance test and data retention test

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Semiconductor Manufacturing, IEEE Transactions on  (Volume:10 ,  Issue: 2 )