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Cell Library Characterization at Low Voltage Using Non-linear Operating Point Analysis of Local Variations

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8 Author(s)
Rahul Rithe ; Massachusetts Inst. of Technol., Cambridge, MA, USA ; Sharon Chou ; Jie Gu ; Alice Wang
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When CMOS is operated at a supply voltage of 0.5V and below, Random Dopant Fluctuations (RDFs) result in a stochastic component of logic delay that can be comparable to the nominal delay. Moreover, the Probability Density Function (PDF) of this stochastic delay can be highly non-Gaussian. The Non-Linear, Operating Point Analysis of Local Variations (NLOPALV) technique has been shown to be accurate and computationally efficient in simulating any point on the delay PDF of a logic Timing Path (TP). This paper applies the NLOPALV approach to characterizing the stochastic delay of logic cells. NLOPALV theory is presented, and NLOPALV is used to characterize a cell library designed in 28 nm CMOS. NLOPALV is accurate to within 5% compared to SPICE-based Monte Carlo analysis.

Published in:

2011 24th Internatioal Conference on VLSI Design

Date of Conference:

2-7 Jan. 2011