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This paper proposes a low-power variation - immune dual-threshold voltage CNFET-based 7T SRAM cell. The proposed CNFET-based 7T SRAM cell offers ~1.2× improvement in standby power, ~1.3× improvement in read delay, ~1.1× improvement in write delay. It offers tighter spread in write access time (1.4× @ OEP (optimum energy point) and 1.2× @ VDD=1 V). It features 56.3% improvement in hold static noise margin and 40% improvement in read static noise margin. All the simulation measurements are taken at proposed OEP decided by the optimum results obtained after extensive simulation on HSPICE environment.