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Multi-objective optimization of NoC standard architectures using Genetic Algorithms

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4 Author(s)
Morgan, A.A. ; Dept. of Electr. & Comput. Eng., Univ. of Victoria, Victoria, BC, Canada ; Elmiligi, H. ; El-Kharashi, M.W. ; Gebali, F.

One of the challenging problems in Networks-on-Chip (NoC) design is optimizing the architectural structure of the on-chip network in order to maximize the network performance while minimizing corresponding costs. In this paper, a methodology for multi-objective optimization of NoC standard architectures using Genetic Algorithms is presented. The methodology considers two cost metrics, power and area, and two performance metrics, delay and reliability. Moreover, our methodology combines the best selection of NoC standard topology, the optimum mapping of application cores onto that topology, and the best routing of application traffic traces over the generated network. The methodology is evaluated by applying it to an NoC benchmark application as a case study. Results show that the architectures generated by our methodology outperform those of other standard architectures customization techniques with respect to power, area, delay, reliability, and the combination of the four metrics.

Published in:

Signal Processing and Information Technology (ISSPIT), 2010 IEEE International Symposium on

Date of Conference:

15-18 Dec. 2010

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