By Topic

Work-function engineering in gate first technology for multi-VT dual-gate FDSOI CMOS on UTBOX

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

33 Author(s)
Weber, O. ; LETI, CEA, Grenoble, France ; Andrieu, F. ; Mazurier, J. ; Casse, M.
more authors

For the first time, we demonstrate low-VT (VTlin ±0.32V) nMOS and pMOS adjusted in a gate first FDSOI technology by work-function engineering of TiN/TaAlN metal gates. Especially, for low-VT pMOS, various Chemical-Vapor-Deposited TaAlN stacks with optimized Al concentration have been studied to finely tune the work-function above midgap while maintaining good reliability and mobility. Short channel performance of 500μA/μm ION and 245μA/μm IEFF at 2nA/μm IOFF and VDD=0.9 V is reported on pMOS with a TaAlN gate. In addition, it is found that the combination of these two metal gates with either n- or p-doped ground planes below the Ultra-Thin Buried Oxide (BOX) can offer 4 different VT from 0.32 V to 0.6 V for both nMOS and pMOS, demonstrating a real multiple-VT capability for FDSOI CMOS while keeping the channel undoped and the VT variability around AVT=1.3mV.μm.

Published in:

Electron Devices Meeting (IEDM), 2010 IEEE International

Date of Conference:

6-8 Dec. 2010