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A 1-V Process-Insensitive Current-Scalable Two-Stage Opamp With Enhanced DC Gain and Settling Behavior in 65-nm Digital CMOS

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2 Author(s)
Taherzadeh-Sani, M. ; Dept. of Electr. & Comput. Eng., McGill Univ., Montreal, QC, Canada ; Hamoui, A.A.

A pseudo-cascode compensation technique is proposed to enable a process-insensitive and current-scalable design of the classical two-stage opamp at low supply voltages, without requiring any additional power dissipation. Furthermore, a bulk-biasing technique is proposed to enhance the dc gain of the two-stage opamp, without affecting its output-voltage swing and without requiring any additional power dissipation. To compare the performance advantages of the proposed pseudo-cascode compensation technique versus classical Miller compensation in a two-stage opamp with/without applying the proposed bulk-biasing technique, four opamps were fabricated on the same die in a 1-V 65-nm CMOS process. The corresponding transistors in all four opamps had equal sizes. Furthermore, all four opamps had equal total compensation capacitance and the same total power dissipation. Accordingly, compared to using Miller compensation, by applying the proposed pseudo-cascode-compensation and bulk-biasing techniques in a two-stage opamp, the opamp's dc gain is increased by a factor of 4 (12 dB), its unit-gain frequency is increased by 40%, and its phase margin is maintained over a factor of 100 scaling in its bias current. Furthermore, the overshoot in its large-signal step response is eliminated and the rise/fall settling times are improved by 33%. The trade-off is a minimal decrease in the opamp's phase margin. Importantly, this is all achieved without affecting the opamp's output-voltage swing and without requiring any additional power dissipation.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:46 ,  Issue: 3 )