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The underlying technologies of web information and distributed systems often require efficient XML parsing. Even though new software-based XML parsing techniques improve XML processing, the verbose nature of XML does not help to achieve the substantial improvements that are desired. In some systems, such as mobile devices, the restricted memory resources exacerbate the problems associated with XML processing. In this paper, we present a novel XML parsing technique-titled SCBXP-that is designed to achieve high performance in hardware-based environments. In addition, the parsing technique provides a natural way of checking for full well formedness and partial validation, thereby taking advantage of our CAM-based architecture and the inherent parallel features of the hardware. Furthermore, the efficiency of XML parsing is maintained even when memory resources are limited. The SCBXP technique architecture makes use of 1) a content-addressable memory that must be configured with a skeleton of the XML document being parsed, 2) a finite state machine that controls FIFOs, in order to align XML data properly, 3) multiple state machines acting on the multilevel nature of XML, and 4) dual-port memory modules. The results of testing the SCBXP technique, implemented on an FPGA, demonstrate that a processing rate of at least 2 bytes of XML data can be performed during each clock cycle.