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Local-Stress-Induced Trap States in SOI Layers With Different Levels of Roughness at SOI/BOX Interfaces

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5 Author(s)
Nakajima, Yoshikata ; Bio-Nano Electron. Res. Center, Toyo Univ., Kawagoe, Japan ; Watanabe, Y. ; Hanajiri, Tatsuro ; Toyabe, Toru
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The authors examined the origins of high-density trap states in silicon-on-insulator (SOI) layers by means of scanning probe microscopy measurements, I-V characteristics in MOSFETs, and micro-Raman measurements in SOI wafers, including bonded wafers and separation by implanted oxygen (SIMOX) wafers having different root-mean-square values of roughness at the SOI/buried oxide (BOX) interface. As a result, it was concluded that nanoscale roughness at the SOI/BOX interface causes local mechanical stress a few tens of nanometers from the interface and that this stress induces the SIMOX-specific high-density trap states for holes as well as for electrons in the SOI layers.

Published in:

Electron Device Letters, IEEE  (Volume:32 ,  Issue: 3 )