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Design of a reversible single precision floating point multiplier based on operand decomposition

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3 Author(s)
Nachtigal, M. ; Dept. of Comput. Sci. & Eng., Univ. of South Florida, Tampa, FL, USA ; Thapliyal, H. ; Ranganathan, N.

Reversible logic is a promising field of research that finds applications in low power computing, quantum computing, optical computing, and other emerging computing technologies. Further, floating point multiplication is one of the major operations in image and digital signal processing applications. The single precision floating-point multiplier requires the design of efficient 24×24 bit integer multiplier. In this work, we propose a new reversible design of single precision floating point multiplier based on operand decomposition approach. To design the reversible 24×24 (A×B) bit multiplier (assume A and B are of 24 bits each), the operands are decomposed into three partitions of 8 bits each. Thus, the 24×24 bit reversible multiplication is performed through nine reversible 8×8 bit Wallace tree multipliers, whose outputs are then summed. We propose a new reversible design of the 8×8 bit Wallace tree multiplier that has been optimized in terms of quantum cost, delay, and number of garbage outputs. Wallace tree multiplication consists of three conceptual stages: Partial product generation, partial product compression using 4:2 compressors, full adders, and half adders, and then the final addition stage to generate the product. In this work we perform optimization at each of these three stages. For the first stage, we have proposed a new generalized reversible partial product generation circuitry. For the second stage we have proposed a new reversible 4:2 compressor design for use in the compression tree. Finally, for the summation stage we have carefully chosen and arranged the reversible half adders and full adders in such a way to yield an efficient multiplier optimized in terms of quantum cost, delay, and garbage outputs. We have also illustrated the reversible design of 24×24 bit multiplier using the proposed 8×8 bit reversible Wallace tree multiplier.

Published in:

Nanotechnology (IEEE-NANO), 2010 10th IEEE Conference on

Date of Conference:

17-20 Aug. 2010