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In this work a new efficient architecture of modulo 2n+1 subtractors for weighted operands is presented. The proposed subtractors are composed of a modified carry save adder with inverted end around carry and a diminished-1 modulo 2n+1 adder. The proposed subtractors are more efficient with respect to both area and delay compared to previously proposed modulo 2n+1 subtractors for weighted operands.
Microelectronics (ICM), 2010 International Conference on
Date of Conference: 19-22 Dec. 2010