Referenced Items are not available for this document.
Pass transistor logic (PTL) circuits are known to be well suited for pipelined circuits and have been receiving considerable interest in recent times. Existing techniques for synthesizing PTL circuits are based on two level networks of transistors. In this paper, we have proposed a new decision diagram based model for multilevel PTL circuits. We have described a number of transformations on our model. Using these transformations, we have developed a top down greedy heuristic for synthesizing PTL circuits and have established that our synthesis techniques give us significant savings compared to existing synthesis procedures
Published in:
VLSI Design, 1997. Proceedings., Tenth International Conference on
Date of Conference: 4-7 Jan 1997
- Page(s):
- 516 - 518
- Meeting Date :
- 04 Jan 1997-07 Jan 1997
- ISSN :
- 1063-9667
- Print ISBN:
- 0-8186-7755-4
- INSPEC Accession Number:
- 5565807
- Conference Location :
- Hyderabad
- Digital Object Identifier :
- 10.1109/ICVD.1997.568191
- Product Type:
- Conference Publications
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