By Topic

Efficient implementation of multiple on-chip signature checking

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Abdulla, M.F. ; Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., New Delhi, India ; Ravikumar, C.P. ; Kumar, A.

Detection latency in a BIST scheme is the delay between the time instant at which a faulty response appears and the time instant at which the fault is detected. Conventional BILBO-BIST schemes suffer from long detection latency since it is not until the signatures are scanned out and compared off-chip that a fault become apparent. Aliasing, which is a fallout of long detection latency, is a serious problem. We have proposed an improved BIST architecture which supports on-chip comparison of multiple signatures to minimize the probability of aliasing and total test time. Also we quantified the aliasing probability of the “Multiple On-chip Signature Comparison scheme” (MOSC) scheme proposed. In this paper, we describe an efficient implementation of the MOSC test architecture and report results on several benchmark circuits. We describe different optimization methods to reduce the overall test control area

Published in:

VLSI Design, 1997. Proceedings., Tenth International Conference on

Date of Conference:

4-7 Jan 1997