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Allocation of FIFO structures in RTL data paths

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2 Author(s)
H. Khanna ; Cadence Design Syst. (I) Pvt. Ltd., Noida, India ; M. Balakrishnan

Along with the functional units, storage and interconnects also contribute significantly to the data path cost. This paper addresses the issue of reducing the storage and interconnect cost by allocating queues for storing variables. In contrast to the earlier works, we support “regular” cdfgs and multi-cycle functional units for queue synthesis. Initial results on HLS benchmark examples have been encouraging and show the potential of data path cost reduction using queue synthesis. A novel feature of our work is the formulation of the problem for a variety of FIFO structures with their own “queueing” criteria

Published in:

VLSI Design, 1997. Proceedings., Tenth International Conference on

Date of Conference:

4-7 Jan 1997