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Fast power integrity estimation method by use of LSI power-pin model

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3 Author(s)
Takashi Harada ; NEC Corporation, 1120, Shimokuzawa, Chuo-ku, Sagamihara, Kanagawa 252-5298, Japan ; Masashi Ogawa ; Manabu Kusumoto

Fast power integrity analysis system to realize the chip-package-board co-design is described. As high-speed signal processing of semiconductor chips and high-density packaging technologies are progressed, circuit margins are reduced and the packaging design becomes difficult more and more. These difficulties often bring re-designs of board and package layouts. Short turn-around-time estimation techniques for analyzing the electrical performance integrating chip-package-board characteristics have been required for reducing the time loss by the rework and increase design efficiency,. This system contributes to the increase of design efficiency in the early product development stage followed by reducing the time loss due to the rework in the development process.

Published in:

2010 IEEE CPMT Symposium Japan

Date of Conference:

24-26 Aug. 2010