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Silicon TSV interposers with embedded capacitors for high performance VLSI packaging

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1 Author(s)
Vodrahalli, N. ; Allvia Technol., Sunnyvale, CA, USA

Miniaturization and higher performance needs of the electronic industry continue to drive technology innovations to achieve increased levels of integration. Through Silicon Via technology along with flip chip technology provides significant improvements over the traditional packaging technologies. Vertical stacking of Silicon dies provides a very attractive way of improving functional density of electronics in addition to potentially providing increased electrical performance. Silicon TSV technology along with die stacking on organic substrate is utilized in forming a Silicon Interposer for VLSI packaging. The benefits of high density routing on the Silicon interposer, along with the matching of Silicon CTE provides a reliable packaging technology for next generation VLSI circuits. Very high value capacitors are embedded on the Silicon interposer for low noise decoupling and thus helping to provide a high performance electrical solution.

Published in:

CPMT Symposium Japan, 2010 IEEE

Date of Conference:

24-26 Aug. 2010