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Large Scale 3D Silicon Interposer Based Interconnection for Next Generation High Performance Computational Systems

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2 Author(s)
Daniel Stevenson ; RTI International, Durham ; Robert Conn

The next few generations of high performance computational hardware and architecture present numerous design challenges. System power must come down, processor to memory and processor to processor bandwidth must go up. To improve performance, distances between components must shrink substantially. Designs featuring the use of large area three dimensional silicon interposer (3DSI) technologies, traditional bare die, and the newest 3DICs of stacked bare die appear able to vastly reduce the size of the electronics of a system as well as reduce power and improve performance. In our view, assembly of bare die on various silicon substrates will play an increasingly important role in addressing many of these issues for exascale computing and other high performance applications that will evolve over the next 5 to 10 years. This article describes how 3DSIs can be used in conjunction with the current generation of available integrated circuits and emerging 3DIC devices to realize this promise.

Published in:

Computer  (Volume:PP ,  Issue: 99 )