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Double patterning lithography is the most likely solution for 32nm and below process nodes due to its cost effectiveness. To enable this technique, layout decomposition is applied to split a layout into two non-conflicting patterns. Nevertheless, this problem is NP-hard in general, especially for layouts with random logic. Thus, high quality results are hard to be achieved in reasonable time. Previously, several graph partitioning techniques have been presented in order to speed up the process, with the tradeoff of the quality of results (QoR). We propose a graph division method that does not have this deficiency. First, we start with a conflict graph derived from a layout. Based on a data structure named SPQR-tree, the graph is divided into its triconnected components in linear time. The solutions of these components are then combined in a way that no QoR is lost. Thus, we call this method a ”lossless” method. Experimental results show that the proposed method can achieve 5X speedup without sacrificing any QoR.