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H.264FRext video coding standard uses integer 8 × 8 discrete cosine transform (DCT) algorithm. It can preserve the detail image information better. Compared with the traditional cosine transform, integer DCT can avoid the mismatch problem, increase the computation speed, and is more feasible for hardware implementation. This paper proposes a novel two-dimension DCT hardware structure based on the fast papilionaceous algorithm and the reusable row and column transform unit. The proposed hardware architecture is described by Verilog HDL language and implemented with SMIC 0.18μm2 technology. Experiments show that the maximum delay of circuit is 2.74833ns after synthesis, and the area of the system is 94283.4844 μm2, which can satisfy the system requirements to both circuit area and speed.