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CPM in CMPs: Coordinated Power Management in Chip-Multiprocessors

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4 Author(s)
Asit K. Mishra ; Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA ; Shekhar Srikantaiah ; Mahmut Kandemir ; Chita R. Das

Multiple clock domain architectures have recently been proposed to alleviate the power problem in CMPs by having different frequency/voltage values assigned to each domain based on workload requirements. However, accurate allocation of power to these voltage/frequency islands based on time varying workload characteristics as well as controlling the power consumption at the provisioned power level is quite non-trivial. Toward this end, we propose a two-tier feedback-based control theoretic solution. Our first-tier consists of a global power manager that allocates power targets to individual islands based on the workload dynamics. The power consumptions of these islands are in turn controlled by a second-tier, consisting of local controllers that regulate island power using dynamic voltage and frequency scaling in response to workload requirements.

Published in:

2010 ACM/IEEE International Conference for High Performance Computing, Networking, Storage and Analysis

Date of Conference:

13-19 Nov. 2010