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Low profile CSP (LP-CSP) technology for ultra-thin IC packaging applications

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5 Author(s)
Umesh Sharma ; ON Semiconductor, Milpitas, CA , USA ; Phil Holland ; Harry Gee ; Lu Ning
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Miniaturization of mobile electronics and consumer devices has resulted in a three dimensional (3D) scaling trend for Wafer Level Chip Scale Packaging (WLCSP) technology. Horizontal scaling and the impact on device reliability have been described in detail in many previous publications. Horizontal scaling typically implies reduction in the I/O pitch leading to a smaller die size. The device reliability measured with respect to temperature-cycling tests and drop tests, improves as the I/O pitch reduces. Scaling rules have been developed for horizontal scaling. In this paper, we discuss the vertical scaling of WLCSP technology that does not follow conventional scaling rules. Aggressive scaling is implemented in the vertical dimension to arrive at a low form factor package technology. Such a packaging technology is extremely useful in space constrained, ultra-thin, consumer electronics products. We discuss the fabrication technology and then present the reliability results. A simple RC filter circuit is used as a test vehicle to compare the performance and reliability of the new LP-CSP process with the conventional CSP process.

Published in:

Electronic System-Integration Technology Conference (ESTC), 2010 3rd

Date of Conference:

13-16 Sept. 2010