An optimizing compiler method to avoid partial invalid PLC instructions

A ladder diagram is read from left to right and top to bottom. The complexity and length of the rungs decide scanning time of a ladder diagram. CPU resources are always seriously occupied by useless instructions when PLC control systems are on the run time, which seriously slow down the system responses. In order to solve this problem, a compilation method is proposed to optimize PLC programme to avoid the execution of partially useless instructions. According to the result of experiments, the performance of PLC system is improved by this method, especially for the ladder diagram containing counter or timer function.