Close category search window
 

The means of the differential amplifier input offset voltage reduction

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)
Baskys, A. ; Dept. of Comput. Eng., VGTU, Vilnius, Lithuania

The input offset voltage of the differential amplifier based on the bipolar junction transistors, which operate at high current density, is analysed in this work. An analytical approach based on the equations in the explicit form is used to determine the input offset voltage reduction means. The obtained results are tested using numerical simulation of the differential amplifier.

Published in:
Electronics Conference (BEC), 2010 12th Biennial Baltic

Date of Conference: 4-6 Oct. 2010

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2013 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.