Notification:
We are currently experiencing intermittent issues impacting performance. We apologize for the inconvenience.
By Topic

Systolic arrays for 2D decimation filters

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Dunstan, N. ; Dept. of Math. Stat. & Comput. Sci., New England Univ., Armidale, NSW, Australia ; Lenders, P.M.

Convolution is required by many image processing procedures such as pattern matching, edge detection and resizing. Decimation filtering is a subset of convolution in that the convolution of an image includes decimation filter products. The paper investigates systolic array designs for two dimensional convolution and designs for dedicated decimation filters. While existing designs for two dimensional convolution are suitable as decimation filters they can be improved by reducing the number of processing cells. A systolic array for convolution/decimation is presented which completes in time proportional to the image size with the array proportional to the window size. The array has optimal latency for the algorithm used. It is derived using a synthesis procedure for multidimensional multirate arrays which includes restricting the size of the array and reducing it from three dimensions to just two

Published in:

Algorithms & Architectures for Parallel Processing, 1996. ICAPP 96. 1996 IEEE Second International Conference on

Date of Conference:

11-13 Jun 1996