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In this letter, a novel post-CMOS silicon-embedded coreless power inductor is proposed and demonstrated. The inductor is fabricated in the thick bottom layer of a silicon substrate and connected to the front side through vias opened in the thin top layer where control circuits can be fabricated for chip area saving. A 0.8- coreless inductor fabricated using this monolithic inductor technology shows a low dc resistance of 87 and an inductance of 13.1 nH with a quality factor of 3.9 at 100 MHz. A high inductor efficiency of 93% was estimated for 2.4-1.5-V 0.6-A power conversion at 100 MHz. This technology is very suitable for power-supply-on-chip applications.
Date of Publication: Jan. 2011