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An 18 b 12.5 MS/s ADC With 93 dB SNR

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5 Author(s)

This paper presents a precision 18-bit 12.5 MS/s ADC that was designed primarily for digital X-ray imaging systems. This ADC was intended to have a faster output data rate than the precision successive approximation ADCs normally chosen for these systems but with similar DC accuracy and dynamic range. The chosen architecture consists of a pipeline of two multi-bit successive approximation converters. The first successive approximation ADC generates an initial coarse conversion result. The DACs within this converter are then used to generate a residue which is amplified by a residue amplifier before being converted by a second successive approximation ADC. Four comparators within each ADC allow 2 bits to be determined each bit trial. Capacitor mismatch errors are digitally corrected with error coefficients stored in non-volatile memory. Dither is used to reduce the effect of errors in the flash ADC within the second ADC. The ADC was implemented on 0.25 m CMOS process with PIP capacitors and achieves a SNR of 93 dB with a 50 kHz input tone. INL and DNL are within LSB and LSB respectively. Power consumption is 105 mW, excluding LVDS interface power.

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Solid-State Circuits, IEEE Journal of  (Volume:45 ,  Issue: 12 )