Skip to Main Content
This work reports on the integration of n-type lateral-drain-extended MOS transistors (LDMOS) in a 0.13 μm SiGe BiCMOS technology. The transistors are realized with no additional process steps using the core dual-gate-oxide CMOS flow only. LDMOS drift regions are formed by compensating lightly-doped drain (LDD) implantations of NMOS and PMOS transistors of the baseline process. Stable operation with less than 10% parameter variations in 10 years is achieved up to operating voltages VDD,max of 10V for devices with breakdown voltages BVDSS = 30V and on-resistances RON = 7.3Ωmm. Devices for different operating voltages VDD,max are realized by layout variations. Devices with VDD,max = 6V demonstrate breakdown voltages BVDSS = 25V, on-resistances RON = 4.9Ωmm, and peak transit frequencies fT = 32 GHz.