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Power-aware, dependable, and high-performance communication link using PCI Express: PEARL

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5 Author(s)
Hanawa, T. ; Grad. Sch. of Syst. & Inf. Eng., Univ. of Tsukuba, Tsukuba, Japan ; Boku, T. ; Miura, S. ; Sato, M.
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We have proposed a power-aware, dependable, and high-performance communication link using PCI Express as a direct communication device, referred to as PEARL for application in a wide range of parallel and distributed systems from high-end embedded systems to small-scale high-performance clusters. The PEACH chip, as a communicator chip for realizing PEARL, concentrates four ports of PCI Express Gen 2 with four lanes, and employs M32R processor with four cores and several DMACs. The network interface card implementing the PEACH chip provides a power-aware, dependable, and highperformance communication link among host nodes. We also present the results of a preliminary evaluation using the PEACH board. As a result of DMA transfer on PCI Express between PEACH boards, the minimum latency was determined to be less than 1 μs, and the maximum bandwidth was 1.1 Gbytes/s for a data size of 256 Kbyte.

Published in:

Cluster Computing Workshops and Posters (CLUSTER WORKSHOPS), 2010 IEEE International Conference on

Date of Conference:

20-24 Sept. 2010