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Design and performance analysis of a low complexity digital clock recovery algorithm for software-defined radio applications

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2 Author(s)
Montazeri, A. ; Dept. of Electr. Eng., Univ. of Texas at Dallas, Richardson, TX, USA ; Kiasaleh, K.

In this paper, we propose and study a low-complexity digital clock recovery scheme suitable for implementation on programmable platforms, such as digital signal processing (DSP) or field-programmable gate-array (FPGA) platforms. Performance is established in terms of mean-square timing error and the required computational complexity, a key factor in the successful implementation of efficient software-defined radios (SDR). It is shown that the proposed algorithm achieves a superior performance when compared with the existing algorithms for a wide range of operating parameters. To assess complexity in terms of resource utilization, the FPGA platform is used to study the proposed algorithm along with other well-known algorithms.

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Consumer Electronics, IEEE Transactions on  (Volume:56 ,  Issue: 3 )