Referenced Items are not available for this document.
A 2.1-to-2.8-GHz low-power consumption all-digital phase locked loop (ADPLL) with a time-windowed time-to-digital converter (TDC) is presented. The time-windowed TDC uses a two-step structure with an inverter- and a Vernier-delay time-quantizer to improve time resolution, which results in low phase noise. Time-windowed operation is implemented in the TDC, in which a single-shot pulse-based operation is used for low power consumption. The test chip implemented in 90-nm CMOS technology exhibits in-band phase noise of , where the loop-bandwidth is set to 500 kHz with a 40-MHz reference signal, and out-band noise of at a 1-MHz offset frequency. The chip core occupies 0.37 and the measured power consumption is 8.1 mA from a 1.2-V power supply.
Published in:
Solid-State Circuits, IEEE Journal of
(Volume:45
,
Issue:
12
)
Date of Publication: Dec. 2010
- Page(s):
- 2582 - 2590
- ISSN :
- 0018-9200
- INSPEC Accession Number:
- 11684825
- Digital Object Identifier :
- 10.1109/JSSC.2010.2076591
- Product Type:
- Journals & Magazines
- Date of Publication :
- 18 October 2010
- Date of Current Version :
- 06 December 2010
- Issue Date :
- Dec. 2010
- Sponsored by :
- IEEE Solid-State Circuits Society
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