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A compact parallel optical receiver consisting of a four-channel 25-Gb/s CMOS transimpedance-amplifier (TIA) array and a PIN-PD array for board-to-board optical interconnects was developed. Both arrays are directly mounted on a multi-layer ceramic package. The 25-Gb/s TIA array was fabricated by using 65-nm CMOS technology. To improve gain flatness and reduce inter-symbol interference caused by insertion loss, a gain-stage amplifier with flat frequency response and a 50-Ω output driver with an analogue equalizer were implemented in the TIA array. The TIA array achieves transimpedance gain of 69.8 dBΩ, bandwidth of 22.8 GHz, and gain flatness of ±2 dB after equalizing the effect of insertion losses at the input and output ports. A compact 100-Gb/s CMOS optical receiver is composed of a four-channel 25-Gb/s PIN-PD and the TIA array mounted on a 16-mm-square multi-layer low-temperature on-fired ceramic (LTCC) package. To alleviate the inner-channel crosstalk, the output signal lines from the PIN-PD array are connected to the TIA array through the coplanar lines, which are sandwiched by the upper and lower ground layers and the right-and-left ground lines. The optical receiver demonstrates negligible inter-channel crosstalk of less than -17 dB at operation frequency up to 25 GHz. Its measured sensitivity for a solitary signal input at 10-12 BER is -8.1 dBm, and its crosstalk between adjacent channels is 0.8 dB. Moreover, its power dissipation is only 3.0 mW/Gb/s at a data rate of 25 Gb/s, and its total power consumption (including that of the equalizer function) is low, i.e., 295 mW.
Date of Publication: Dec.1, 2010