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Design-kit development based upon ISsiT's CMOS 1µM process technology

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6 Author(s)
Chenouf, A. ; Adv. Technol. Dev. Centre, CDTA, Microelectron. & Nanotechnol. Lab., Algiers, Algeria ; Slimane, A. ; Berrandjia, M.L. ; Oudjida, A.K.
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This paper summarizes the necessary steps we went through to develop a design-kit for full-custom design based upon ISiT's CMOS 1 μm technology process. All basic information dealing with technology setup, rule decks and analog simulation environment is provided and commented. The design-kit is fully compliant with Cadence Generic Process Design-Kit (GPDK) methodology guide, revision 1.8, September 2002. It has been developed using Cadence IC-Package IC5.1.41 tool-chain version, running under Solaris 10 OS. To validate our design-kit, an inverter cell has been designed according to the standard full-custom design flow.

Published in:

Systems Signals and Devices (SSD), 2010 7th International Multi-Conference on

Date of Conference:

27-30 June 2010