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A 3 Watt 39.8–44.6 Gb/s Dual-Mode SFI5.2 SerDes Chip Set in 65 nm CMOS

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23 Author(s)
Nedovic, Nikola ; Fujitsu Labs. of America, Sunnyvale, CA, USA ; Kristensson, A. ; Parikh, S. ; Reddy, S.
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A Dual-mode 2 ×21.5-22.3 Gb/s DQPSK or 1 × 39.8-44.6 Gb/s NRZ to 4 × 9.95-11.2 Gb/s SFI5.2-compliant two-chip SerDes for a family of 40 Gb/s optical transponders has been fabricated in 65 nm 12-metal CMOS. By demultiplexing to 16 × 2.5 Gb/s internally, all logic and testability functions could be implemented in standard-cell CMOS, resulting in total power consumption of 3 W, 75 % lower than commercial BiCMOS SFI5 40 Gb/s SerDes ICs. Chip area is 4 × 4 mm, and the ICs are flip-chip mounted into a quad flat-pack package.

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Solid-State Circuits, IEEE Journal of  (Volume:45 ,  Issue: 10 )