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30% productivity increase of 16 Mb-DRAM gate-conductor etching without additional investment

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2 Author(s)
U. Rogatty ; SIEMENS SA, Corbeil-Essonnes, France ; F. G. Boebel

For today high volume 16 Mb-DRAM manufacturing process optimization and increase of tool utilization is a key importance to gain maximum productivity. The authors show in detail how they achieved a 30% productivity increase for the gate conductor etch process. Special emphasis was put on the methodology used for analysis of process, process-flow and tool set. The modified process steps are explained in detail. The careful analysis of a clustered 4 chamber AMAT P5000 MarkII etch process (Capoxide/Wsix/Strip/Poly) showed that the maximum throughput was gated by the slowest single raw process time (RTP). By declustering the process, we were able to rearrange the number of etch chambers according to the RPT of each single etch step and therefore the utilisation of the available etch chambers was optimized. A further improvement was achieved by modifying the WSix etch process, introducing a HARDMASK and moving the resist-strip on stand-alone FUSION and FSI tools, which were used in another process as well. This paper shows that due to the declustered process. The combined uptime of the 4-chamber etch tools was increased. All combined improvements gave a productivity increase and improved wafer throughput of about 30% compared to the situation before. The capital investment was less than 300K$ and no further etch tools had to be purchased

Published in:

Advanced Semiconductor Manufacturing Conference and Workshop, 1996. ASMC 96 Proceedings. IEEE/SEMI 1996

Date of Conference:

12-14 Nov 1996