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PRESENT, proposed by A. Bogdanov et al. in CHES 2007, is an ultra-lightweight symmetric cipher for extremely constrained environments such as RFID tags and sensor networks. In this article, a representative platform, 0.25 μm 1.8 V standard cell circuit is proposed to complement the PRESENT, the simulation-based ASIC experimental environment is built to acquire power data. According to the fact that the power consumption of a digital circuit implemented in the CMOS technology depends on the data that the circuit is processing, we create the hypothetical circuit model for differential power analysis (DPA) against the special block cipher, PRESENT. Two Different statistical methods, multi-bit DPA and correlation power analysis (CPA), are conducted in this paper to analyze the power data sampled from the power traces. We can attack all secret key bits after first two rounds DPA attack. Our results present the vulnerability to power analysis attack against the hardware implementations of PRESENT.