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This paper presents a research and design method of plug-type IP information monitoring equipment based on parallel algorithm. It mainly uses the Ethernet hub and field-programmable gate array (FPGA) technology to implement the detection and management of full-duplex IP datagram. Meanwhile using time interval as a judge to analyze and process IP datagram. By detecting, the device can meet the design requirements, with the characteristic of real-time, not to delay the network speed, not take up IP addresses, and low cost.
Date of Conference: 20-22 Aug. 2010