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Dynamic SRAM stability characterization in 45nm CMOS

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3 Author(s)
Seng Oon Toh ; Dept. of Electrical Engineering and Computer Sciences, University of California, Berkeley 94720, USA ; Zheng Guo ; Borivoje Nikolić

A method for characterizing dynamic SRAM stability using pulsed wordlines, is demonstrated in 45nm CMOS. Static read margins were observed to overestimate failures by up to 1000x while static write margins failed to predict outliers in dynamic write stability. Dynamic write stability was demonstrated to exhibit an enhanced sensitivity to process variations, and negative bias temperature instability (NBTI), compared to static write margins.

Published in:

2010 Symposium on VLSI Circuits

Date of Conference:

16-18 June 2010