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This study presents a single-event upset (SEU) hardened latch having first and second cross-coupled inverters and first and second programmable resistance metallisation cells. The metallisation cells may be programmed to low or high-resistance states. When set to a low-resistance state, the latch may be accessed to write a new logic state into the latch. When reset to a high-resistance state, the latch is in a radiation-hard state, thereby preventing the latch from getting affected by SEUs. This technique introduces little layout penalty, does not adversely affect circuit speed and is simple to implement in conventional semiconductor manufacturing process flow.