By Topic

Low-overhead single-event upset hardened latch using programmable resistance cells

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $31
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
She, X. ; State Key Lab. of ASIC & Syst., Fudan Univ., Shanghai, China ; Li, N.

This study presents a single-event upset (SEU) hardened latch having first and second cross-coupled inverters and first and second programmable resistance metallisation cells. The metallisation cells may be programmed to low or high-resistance states. When set to a low-resistance state, the latch may be accessed to write a new logic state into the latch. When reset to a high-resistance state, the latch is in a radiation-hard state, thereby preventing the latch from getting affected by SEUs. This technique introduces little layout penalty, does not adversely affect circuit speed and is simple to implement in conventional semiconductor manufacturing process flow.

Published in:

Computers & Digital Techniques, IET  (Volume:4 ,  Issue: 5 )