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Robust intellectual property protection of VLSI physical design

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2 Author(s)
D. Saha ; Advanced Computing and Microelectronics Unit, Indian Statistical Institute, Kolkata, India ; S. Sur-Kolay

In deep sub-micron VLSI, increased demand for design productivity of ICs with millions of devices has led to widespread design reuse. This however enhances the probability of infringement of intellectual property (IP) of the design. Typically, repudiation attack by the IP owner through challenging the legality of the buyer and additive attack through insertion of additional marks in the design are not considered in the design cycle. Moreover, public watermark verification is still not secure, as attacker manages to override the mark with his own one. Our proposed algorithm ROBUST_IP tackles these issues with a modified IP marking schema. Firstly, it introduces a master key of an independent intellectual property protection (IPP) team to eliminate the scope of repudiation attack, renders insertion of fake marks useless and can efficiently extract the signatures of legal IP owner and buyer in absence of any claim. Secondly, the concept of a new parameter, public_verification_count, enhances security during public mark verification. Finally, novel techniques based on this schema are proposed to embed marks in the physical design phase specifically for ASIC and FPGA design. Experimental results on MCNC benchmarks demonstrate that removal/tampering of marks remain infeasible at the cost of insignificant overhead in area/delay.

Published in:

IET Computers & Digital Techniques  (Volume:4 ,  Issue: 5 )