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Key elements of systematic yield optimization used for SOI 90, 65 & 45nm microprocessors performing between 1.5 - 5 GHz (Table 1) will be reviewed. A method for isolating, measuring and acting upon systematic yield elements is shown. Models for optimizing performance limited yield and optimizing FET performance for maximum yield are reviewed. Finally, techniques for ship product quality level yield optimization are shown.
Date of Conference: 11-13 July 2010